Introduction

User Guide update history

2021.12.24

  • Initial Draft

2021.12.29

  • Added FGATI test boards (Hardware)

  • Added firmware and software links to Open-It page (Software and Practical Usage).

Module overview

Kalliope (KEK Advanced Linear and Logic boards Integrated for Optical detectors for Positrons and Electrons) is a compact Time to Digital Converter (TDC) unit with 1 ns timing resolution, developed for muon-related measurements in Materials and Life science Experiment Facility (MLF), J-PARC. One Kalliope unit provides 32 channel inputs. Kalliope consists of two major components: digital board with field programmable gate array (FPGA) and analog board with application spcific integrated circuit (ASIC), in addition to the detector boards, which usually have solid state optical detectors, such as Multi-Pixel Photon Counter (MPPC) by Hamamatsu Photonics, Ltd.

The FPGA which controls digital board is Xilinx Spartan 6 (XC6SLX100T-2FGG484C), which is rather outdated nowadays, but still provides stable operations. The ASIC on the analog board provides amplification, shaping and discrimination (ASD) of input analog signals. There are two version of ASICs currently employed: Volume2012 and Volume2014. The ASD characteristics are different between these two, and used for different applications. For muon experiments in pulsed source, Volume2014 provides a better time structure for the multi-hit signals. However, the rise time of Volume2012 is faster than Volume2014, and advantageous in applications for continuous muon source or neutron time of flight (TOF) measurements, where the second hit within a few hundred nanoseconds is not relevant. The voltage amplifier employed in Volume2012 has an undershoot at ~300 ns, manifesting a spectral distortion in pulsed muon experiments. A newer ASIC, called FGATI, is being developed, which seeks for a faster rise-time than Volume2012 and without a significant after effect. Some firmware on Kalliope digital board controls FGATI for its characteristic test.

Kalliope digital board is equipped with a data communication gigabit ethernet (GbE) interface and one trigger NIM signal input. Communication to the data acquisition (DAQ) PC employs UDP and TCP protocols supplied by the SiTCP technology, which is a FPGA-based hardware implimentation of TCP/IP communications. Kalliope firmware supports 1 Gbps TCP communication via an ethernet cable (Cat.5e and above) or an optical fiber (Multi-mode 850nm). The ethernet interface is provided by Small Form-factor Pluggable (SFP), and metal or optical interfaces may be selected. UDP communication is extended by remote-bus control protocol (RBCP) of SiTCP, which supports the addressed access to the memory region of FPGA to control behavior of Kalliope devices.

Kalliope is developped in an Open-It project Kalliope (MPPC-TDC-SiTCP), employing the technological developments achieved in the Open-It consourtium. The interectual property and its usage is subject to the terms of the Open-It consourtium. Open-It